ARM Cortex-A76 Core User Manual

Chapter A4
Power management
This chapter describes the power domains and the power modes in the Cortex-A76 core.
It contains the following sections:
• A4.1 About power management on page A4-46.
• A4.2 Voltage domains on page A4-47.
• A4.3 Power domains on page A4-48.
• A4.4 Architectural clock gating modes on page A4-50.
• A4.5 Power control on page A4-52.
• A4.6 Core power modes on page A4-53.
• A4.7 Encoding for power modes on page A4-56.
• A4.8 Power domain states for power modes on page A4-57.
• A4.9 Power up and down sequences on page A4-58.
• A4.10 Debug over powerdown on page A4-59.
100798_0300_00_en
Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
A4-45
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core