ARM Cortex-A76 Core User Manual

D9.71 TRCTSCTLR, Global Timestamp Control Register
The TRCTSCTLR controls the insertion of global timestamps in the trace streams. When the selected
event is triggered, the trace unit inserts a global timestamp into the trace streams. The event is selected
from one of the Resource Selectors.
Bit field descriptions
The TRCTSCTLR is a 32-bit register.
31 08 7
SEL
36 4
TYPE
RES0
Figure D9-68 TRCTSCTLR bit assignments
RES0, [31:8]
RES0 Reserved.
TYPE, [7]
Single or combined resource selector.
RES0, [6:4]
RES0 Reserved.
SEL, [3:1]
Identifies the resource selector to use.
Bit fields and details not provided in this description are architecturally defined. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The TRCTSCTLR can be accessed through the external debug interface, offset 0x030.
D9 ETM registers
D9.71 TRCTSCTLR, Global Timestamp Control Register
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core