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B4.2 AArch64 physical GIC CPU interface system register summary

The following table lists the AArch64 physical GIC CPU interface system registers that have

IMPLEMENTATION DEFINED bits.

See the Arm

Generic Interrupt Controller Architecture Specification for more information and a

complete list of AArch64 physical GIC CPU interface system registers.

Table B4-2 AArch64 physical GIC CPU interface system register summary

Name Op0 Op1 CRn CRm Op2 Type Description

ICC_AP0R0_EL1 3 0 12 8 4 RW B4.3 ICC_AP0R0_EL1, Interrupt Controller Active Priorities Group 0

ICC_AP1R0_EL1 3 0 12 9 0 RW B4.4 ICC_AP1R0_EL1, Interrupt Controller Active Priorities Group 1

ICC_BPR0_EL1 3 0 12 8 3 RW B4.5 ICC_BPR0_EL1, Interrupt Controller Binary Point Register 0,

EL1 on page B4-317

ICC_BPR1_EL1 3 0 12 12 3 RW B4.6 ICC_BPR1_EL1, Interrupt Controller Binary Point Register 1,

EL1 on page B4-318

ICC_CTLR_EL1 3 0 12 12 4 RW B4.7 ICC_CTLR_EL1, Interrupt Controller Control Register, EL1

on page B4-319

ICC_CTLR_EL3 3 6 12 12 4 RW B4.8 ICC_CTLR_EL3, Interrupt Controller Control Register, EL3

on page B4-321

ICC_SRE_EL1 3 0 12 12 5 RW B4.9 ICC_SRE_EL1, Interrupt Controller System Register Enable

ICC_SRE_EL2 3 4 12 9 5 RW B4.10 ICC_SRE_EL2, Interrupt Controller System Register Enable

ICC_SRE_EL3 3 6 12 12 5 RW B4.11 ICC_SRE_EL3, Interrupt Controller System Register Enable

B4 GIC registers

B4.2 AArch64 physical GIC CPU interface system register summary

reserved.

B4-314

Non-Confidential

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