ARM Cortex-A76 Core

Chapter A5
Memory Management Unit
This chapter describes the Memory Management Unit (MMU) of the Cortex-A76 core.
It contains the following sections:
• A5.1 About the MMU on page A5-62.
• A5.2 TLB organization on page A5-64.
• A5.3 TLB match process on page A5-65.
• A5.4 Translation table walks on page A5-66.
• A5.5 MMU memory accesses on page A5-67.
• A5.6 Specific behaviors on aborts and memory attributes on page A5-68.
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A5-61
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