B2.57 ID_AA64ISAR1_EL1, AArch64 Instruction Set Attribute Register 1, EL1
The ID_AA64ISAR1_EL1 provides information about the instructions implemented in AArch64 state.
Bit field descriptions
ID_AA64ISAR1_EL1 is a 64-bit register, and is part of the Identification registers functional group.
This register is Read Only.
63 0
DC CVAP
4 320 19
LRCPC
2324
RES0
Figure B2-41 ID_AA64ISAR1_EL1 bit assignments
RES0, [63:24]
RES0 Reserved.
LRCPC, [23:20]
Indicates whether load-acquire (LDA) instructions are implemented for a Release Consistent core
consistent RCPC model.
0x1 The LDAPRB, LDAPRH, and LDAPR instructions are implemented in AArch64.
RES0, [19:4]
RES0 Reserved.
DC CVAP, [3:0]
Indicates whether Data Cache, Clean to the Point of Persistence (DC CVAP) instructions are
implemented.
0x1 DC CVAP is supported in AArch64.
Configurations
There are no configuration notes.
Bit fields and details that are not provided in this description are architecturally defined. See the
Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
B2 AArch64 system registers
B2.57 ID_AA64ISAR1_EL1, AArch64 Instruction Set Attribute Register 1, EL1
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B2-221
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