ARM Cortex-A76 Core User Manual

B2.68 ID_ISAR3_EL1, AArch32 Instruction Set Attribute Register 3, EL1
The ID_ISAR3_EL1 provides information about the instruction sets implemented by the core in
AArch32.
Bit field descriptions
ID_ISAR3_EL1 is a 32-bit register, and is part of the Identification registers functional group.
This register is Read Only.
TabBranch
31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0
T32Copy SVC SaturateT32EE SynchPrim SIMDTrueNOP
Figure B2-52 ID_ISAR3_EL1 bit assignments
T32EE, [31:28]
Indicates the implemented T32EE instructions:
0x0 None implemented.
TrueNOP, [27:24]
Indicates support for True NOP instructions:
0x1 True NOP instructions in both the A32 and T32 instruction sets, and additional NOP-
compatible hints.
T32Copy, [23:20]
Indicates the support for T32 non flag-setting MOV instructions:
0x1 Support for T32 instruction set encoding T1 of the MOV (register) instruction, copying
from a low register to a low register.
TabBranch, [19:16]
Indicates the implemented Table Branch instructions in the T32 instruction set.
0x1 The TBB and TBH instructions.
SynchPrim, [15:12]
Indicates the implemented Synchronization Primitive instructions:
0x2 • The LDREX and STREX instructions.
• The CLREX, LDREXB, STREXB, and STREXH instructions.
• The LDREXD and STREXD instructions.
SVC, [11:8]
Indicates the implemented SVC instructions:
0x1 The SVC instruction.
SIMD, [7:4]
Indicates the implemented Single Instruction Multiple Data (SIMD) instructions.
B2 AArch64 system registers
B2.68 ID_ISAR3_EL1, AArch32 Instruction Set Attribute Register 3, EL1
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B2-239
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core