B2.68 ID_ISAR3_EL1, AArch32 Instruction Set Attribute Register 3, EL1
The ID_ISAR3_EL1 provides information about the instruction sets implemented by the core in
AArch32.
Bit field descriptions
ID_ISAR3_EL1 is a 32-bit register, and is part of the Identification registers functional group.
This register is Read Only.
TabBranch
31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0
T32Copy SVC SaturateT32EE SynchPrim SIMDTrueNOP
Figure B2-52 ID_ISAR3_EL1 bit assignments
T32EE, [31:28]
Indicates the implemented T32EE instructions:
0x0 None implemented.
TrueNOP, [27:24]
Indicates support for True NOP instructions:
0x1 True NOP instructions in both the A32 and T32 instruction sets, and additional NOP-
compatible hints.
T32Copy, [23:20]
Indicates the support for T32 non flag-setting MOV instructions:
0x1 Support for T32 instruction set encoding T1 of the MOV (register) instruction, copying
from a low register to a low register.
TabBranch, [19:16]
Indicates the implemented Table Branch instructions in the T32 instruction set.
0x1 The TBB and TBH instructions.
SynchPrim, [15:12]
Indicates the implemented Synchronization Primitive instructions:
0x2 • The LDREX and STREX instructions.
• The CLREX, LDREXB, STREXB, and STREXH instructions.
• The LDREXD and STREXD instructions.
SVC, [11:8]
Indicates the implemented SVC instructions:
0x1 The SVC instruction.
SIMD, [7:4]
Indicates the implemented Single Instruction Multiple Data (SIMD) instructions.
B2 AArch64 system registers
B2.68 ID_ISAR3_EL1, AArch32 Instruction Set Attribute Register 3, EL1
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B2-239
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