ARM Cortex-A76 Core User Manual

B2.83 MDCR_EL3, Monitor Debug Configuration Register, EL3
The MDCR_EL3 provides configuration options for Security to self-hosted debug.
Bit field descriptions
MDCR_EL3 is a 32-bit register, and is part of:
• The Debug registers functional group.
• The Security registers functional group.
31 0
TPM
20 192122 16 151718 14 13 11 10 9 678 5
TDA
TDOSASPD32
SDD
SPME
EDAD
EPMAD
RES0
Figure B2-67 MDCR_EL3 bit assignments
EPMAD, [21]
External debugger access to Performance Monitors registers disabled. This disables access to
these registers by an external debugger. The possible values are:
0 Access to Performance Monitors registers from external debugger is permitted.
1 Access to Performance Monitors registers from external debugger is disabled, unless
overridden by authentication interface.
EDAD, [20]
External debugger access to breakpoint and watchpoint registers disabled. This disables access
to these registers by an external debugger. The possible values are:
0 Access to breakpoint and watchpoint registers from external debugger is permitted.
1 Access to breakpoint and watchpoint registers from external debugger is disabled,
unless overridden by authentication interface.
SPME, [17]
Secure performance monitors enable. This enables event counting exceptions from Secure state.
The possible values are:
0 Event counting prohibited in Secure state.
1 Event counting allowed in Secure state.
SPD32, [15:14]
RES0
Reserved.
TDOSA, [10]
Trap accesses to the OS debug system registers, OSLAR_EL1, OSLSR_EL1, OSDLR_EL1, and
DBGPRCR_EL1 OS.
0 Accesses are not trapped.
1 Accesses to the OS debug system registers are trapped to EL3.
The reset value is UNKNOWN.
B2 AArch64 system registers
B2.83 MDCR_EL3, Monitor Debug Configuration Register, EL3
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B2-264
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core