ARM Cortex-A76 Core

B2.36 ERRIDR_EL1, Error ID Register, EL1
The ERRIDR_EL1 defines the number of error record registers.
Bit field descriptions
ERRIDR_EL1 is a 32-bit register, and is part of the registers Reliability, Availability, Serviceability
(RAS) functional group.
This register is Read Only.
31 01516
NUM
RES0
Figure B2-32 ERRIDR_EL1 bit assignments
RES0, [31:16]
RES0 Reserved.
NUM, [15:0]
Number of records that can be accessed through the Error Record system registers.
0x0002 Two records present.
Configurations
There are no configuration notes.
Bit fields and details not provided in this description are architecturally defined. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
B2 AArch64 system registers
B2.36 ERRIDR_EL1, Error ID Register, EL1
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B2-196
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