D9.60 TRCPRGCTLR, Programming Control Register
The TRCPRGCTLR enables the ETM trace unit.
Bit field descriptions
The TRCPRGCTLR is a 32-bit register.
31 1 0
EN
RES0
Figure D9-57 TRCPRGCTLR bit assignments
RES0, [31:1]
RES0 Reserved.
EN, [0]
Trace program enable:
0 The ETM trace unit interface in the core is disabled, and clocks are enabled only when
necessary to process APB accesses, or drain any already generated trace. This is the
reset value.
1 The ETM trace unit interface in the core is enabled, and clocks are enabled. Writes to
most trace registers are ignored.
Bit fields and details not provided in this description are architecturally defined. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The TRCPRGCTLR can be accessed through the external debug interface, offset 0x004.
D9 ETM registers
D9.60 TRCPRGCTLR, Programming Control Register
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
D9-570
Non-Confidential
To Next Page
Loading...
