ARM Cortex-A76 Core

B2.26 CPUECTLR_EL1, CPU Extended Control Register, EL1
The CPUECTLR_EL1 provides additional IMPLEMENTATION DEFINED configuration and control options for
the core.
Bit field descriptions
CPUECTLR_EL1 is a 64-bit register, and is part of the 64-bit registers functional group.
This register resets to value 0x0000000961563000.
031
RES0
5678911
EXTLLC
11719 182021222324
DTLB_CABT_EN
WS_THR_L2
WS_THR_L3
WS_THR_L4
WS_THR_DRAM
34
WS_THR_DCZVA
1516
63
3233
ATOMIC_ACQ_NEAR
3638 373940414243
MM_VMID_THR
MM_ASP_EN
MM_CH_DIS
MXP_EN
MXP_TP
MXP_ATHR
3435
62 61 60 59 57 5456 53 525558 51 4950 47 4648 45 44
27 262830 29 25 14 13 12
MM_TLBPF_DIS
CA_EVICT_DIS
CA_UCLEAN_EVICT_EN
PFT_IF
PFT_LS
PFT_MM
L2_FLUSH
HPA_MODE
HPA_CAP
HPA_L1_DIS
HPA_DIS
ATOMIC_ST_NEAR
ATOMIC_REL_NEAR
ATOMIC_LD_NEAR
TLD_PRED_DIS
PF_STS_DIS
PF_SS_L2_DIST
PF_STI_DIS
PF_DIS
RPF_LO_CONF
RPF_DIS
2
RPF_PHIT_EN
Figure B2-22 CPUECTLR_EL1 bit assignments
RES0, [63:62]
RES0 Reserved.
MXP_EN, [61]
Max-power throttle enable. The possible values are:
0 Disables max-power throttling mechanism. This is the reset value.
B2 AArch64 system registers
B2.26 CPUECTLR_EL1, CPU Extended Control Register, EL1
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B2-172
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