ARM Cortex-A76 Core - Page 171

<systemreg> Control Accessibility
E2H TGE NS EL0 EL1 EL2 EL3
S3_0_C15_C0_0 x x 0 - RO n/a RO
S3_0_C15_C0_0 x 0 1 - RO RO RO
S3_0_C15_C0_0 x 1 1 - n/a RO RO
'n/a' Not accessible. The PE cannot be executing at this Exception level, so this access is not possible.
B2 AArch64 system registers
B2.25 CPUCFR_EL1, CPU Configuration Register, EL1
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B2-171
Non-Confidential