ARM Cortex-A76 Core User Manual

A2.1 Components
In a standalone configuration, the core consists of up to four cores and a DSU that connects the cores to
an external memory system.
For more information about the DSU, see the Arm
®
DynamIQ
™
Shared Unit Technical Reference Manual.
The main components of the Cortex-A76 core are:
• Instruction fetch.
• Instruction decode.
• Register rename.
• Instruction issue.
• Execution pipelines.
• L1 data memory system.
• L2 memory system.
A2 Technical overview
A2.1 Components
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reserved.
A2-34
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core