ARM Cortex-A76 Core User Manual

B4.23 ICH_VTR_EL2, Interrupt Controller VGIC Type Register, EL2
ICH_VTR_EL2 reports supported GIC virtualization features.
Bit field descriptions
ICH_VTR_EL2 is a 32-bit register and is part of:
• The GIC system registers functional group.
• The Virtualization registers functional group.
• The GIC host interface control registers functional group.
31
0
5
1823
RES0
4
21
PRIbits
20
ListRegs
29
PREbits
28 26 25
IDbits
22 19
TDS
nV4
A3V
SEIS
Figure B4-13 ICH_VTR_EL2 bit assignments
PRIbits, [31:29]
Priority bits. The number of virtual priority bits implemented, minus one.
0x4 Priority implemented is 5-bit.
PREbits, [28:26]
The number of virtual preemption bits implemented, minus one. The value is:
0x4 Virtual preemption implemented is 5-bit.
IDbits, [25:23]
The number of virtual interrupt identifier bits supported. The value is:
0x0 Virtual interrupt identifier bits that are implemented is 16-bit.
SEIS, [22]
SEI Support. The value is:
0x0 The virtual CPU interface logic does not support generation of SEIs.
A3V, [21]
Affinity 3 Valid. The value is:
0x1 The virtual CPU interface logic supports non-zero values of Affinity 3 in SGI
generation System registers.
nV4, [20]
Direct injection of virtual interrupts not supported. The value is:
0x0 The CPU interface logic supports direct injection of virtual interrupts.
TDS, [19]
B4 GIC registers
B4.23 ICH_VTR_EL2, Interrupt Controller VGIC Type Register, EL2
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core