ARM Cortex-A76 Core User Manual

C3.4 AMU events
The following table describes the counters that are implemented in the Cortex-A76 core and the mapping
to fixed and programmable events.
Table C3-1 Mapping of counters to fixed events
Activity
monitor
counter <n>
Event
type
Event Event
number
Description
0 Fixed Cycles at core
frequency
0x11
Cycles count.
1 Fixed Cycles at constant
frequency
0xEF
This counter is used to replicate the generic system counter that is
incremented on a constant basis, and not incremented depending on
the PE frequency core.
2 Fixed Instructions retired
0x08
Instruction architecturally executed. This counter increments for
every instruction that is executed architecturally, including
instructions that fail their condition code check.
3 Fixed First miss
0xF0
The first miss event tracks whether any external load miss is
outstanding and starts counting only from a first-miss until data
returns for that miss. The counter does not count for any remaining
part of overlapping accesses, only counting again when the first-
miss condition is re-detected.
4 Fixed High activity
0xF1
Instructions executing through the design which act as a hint for
potential high power activity.
C3 Activity Monitor Unit
C3.4 AMU events
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C3-389
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core