ARM Cortex-A76 Core User Manual

B3.7 ERR0PFGCDNR, Error Pseudo Fault Generation Count Down Register
ERR0PFGCDNR is the Cortex-A76 node register that generates one of the errors that are enabled in the
corresponding ERR0PFGCTL register.
Bit field descriptions
ERR0PFGCDNR is a 32-bit register and is RW.
31
0
CDN
Figure B3-5 ERR0PFGCDNR bit assignments
CDN, [31:0]
Count Down value. The reset value of the Error Generation Counter is used for the countdown.
Configurations
There are no configuration options.
ERR0PFGCDNR resets to UNKNOWN.
When ERRSELR.SEL==0, ERR0PFGCDNR is accessible from B2.43 ERXPFGCDNR_EL1,
Selected Error Pseudo Fault Generation Count Down Register, EL1 on page B2-203.
B3 Error system registers
B3.7 ERR0PFGCDNR, Error Pseudo Fault Generation Count Down Register
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core