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ARM Cortex-A76 Core

ARM Cortex-A76 Core
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D9.4 TRCAUTHSTATUS, Authentication Status Register
The TRCAUTHSTATUS indicates the current level of tracing permitted by the system.
Bit field descriptions
The TRCAUTHSTATUS is a 64-bit register.
31 1 0
SNID
2
SID
4 357 68
NSNID
NSID
RES0
Figure D9-3 TRCAUTHSTATUS bit assignments
RES0, [31:8]
RES0 Reserved.
SNID, [7:6]
Secure Non-invasive Debug:
0b10 Secure Non-invasive Debug implemented but disabled.
0b11 Secure Non-invasive Debug implemented and enabled.
SID, [5:4]
Secure Invasive Debug:
0b00 Secure Invasive Debug is not implemented.
NSNID, [3:2]
Non-secure Non-invasive Debug:
0b10 Non-secure Non-invasive Debug implemented but disabled, NIDEN=0.
0b11 Non-secure Non-invasive Debug implemented and enabled, NIDEN=1.
NSID, [1:0]
Non-secure Invasive Debug:
0b00 Non-secure Invasive Debug is not implemented.
Bit fields and details not provided in this description are architecturally defined. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The TRCAUTHSTATUS can be accessed through the external debug interface, offset 0xFB8.
D9 ETM registers
D9.4 TRCAUTHSTATUS, Authentication Status Register
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
D9-502
Non-Confidential

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