ARM Cortex-A76 Core User Manual

D9.28 TRCEXTINSELR, External Input Select Register
The TRCEXTINSELR controls the selectors that choose an external input as a resource in the ETM trace
unit. You can use the Resource Selectors to access these external input resources.
Bit field descriptions
31 08 716 1524 23
SEL2 SEL1 SEL0SEL3
2829 2021 1213 45
RES0
Figure D9-26 TRCEXTINSELR bit assignments
RES0, [31:29]
RES0 Reserved.
SEL3, [28:24]
Selects an event from the external input bus for External Input Resource 3.
RES0, [23:21]
RES0 Reserved.
SEL2, [20:16]
Selects an event from the external input bus for External Input Resource 2.
RES0, [15:13]
RES0 Reserved.
SEL1, [12:8]
Selects an event from the external input bus for External Input Resource 1.
RES0, [7:5]
RES0 Reserved.
SEL0, [4:0]
Selects an event from the external input bus for External Input Resource 0.
Bit fields and details not provided in this description are architecturally defined. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The TRCEXTINSELR can be accessed through the external debug interface, offset 0x120.
D9 ETM registers
D9.28 TRCEXTINSELR, External Input Select Register
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core