B5.4 MVFR0_EL1, Media and VFP Feature Register 0, EL1
The MVFR0_EL1 describes the features provided by the AArch64 Advanced SIMD and floating-point
implementation.
Bit field descriptions
MVFR0_EL1 is a 32-bit register.
SIMDReg
31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0
FPRound FPShVec FPSqrt FPDivide FPTrap FPDP FPSP
Figure B5-3 MVFR0_EL1 bit assignments
FPRound, [31:28]
Indicates the rounding modes supported by the floating-point hardware:
0x1 All rounding modes supported.
FPShVec, [27:24]
Indicates the hardware support for floating-point short vectors:
0x0 Not supported.
FPSqrt, [23:20]
Indicates the hardware support for floating-point square root operations:
0x1 Supported.
FPDivide, [19:16]
Indicates the hardware support for floating-point divide operations:
0x1 Supported.
FPTrap, [15:12]
Indicates whether the floating-point hardware implementation supports exception trapping:
0x0 Not supported.
FPDP, [11:8]
Indicates the hardware support for floating-point double-precision operations:
0x2 Supported, VFPv3 or greater.
See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile for more
information.
FPSP, [7:4]
Indicates the hardware support for floating-point single-precision operations:
0x2 Supported, VFPv3 or greater.
See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile for more
information.
SIMDReg, [3:0]
Indicates support for the Advanced SIMD register bank:
B5 Advanced SIMD and floating-point registers
B5.4 MVFR0_EL1, Media and VFP Feature Register 0, EL1
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B5-351
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