ARM Cortex-A76 Core User Manual

D9.35 TRCIDR8, ID Register 8
The TRCIDR8 returns the maximum speculation depth of the instruction trace stream.
Bit field descriptions
The TRCIDR8 is a 32-bit register.
31 0
MAXSPEC
Figure D9-33 TRCIDR8 bit assignments
MAXSPEC, [31:0]
The maximum number of P0 elements in the trace stream that can be speculative at any time.
0 Maximum speculation depth of the instruction trace stream.
Bit fields and details not provided in this description are architecturally defined. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The TRCIDR8 can be accessed through the external debug interface, offset 0x180.
D9 ETM registers
D9.35 TRCIDR8, ID Register 8
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D9-545
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core