ARM Cortex-A76 Core User Manual

B4.7 ICC_CTLR_EL1, Interrupt Controller Control Register, EL1
ICC_CTLR_EL1 controls aspects of the behavior of the GIC CPU interface and provides information
about the features implemented.
Bit field descriptions
ICC_CTLR_EL1 is a 32-bit register and is part of:
• The GIC system registers functional group.
• The GIC control registers functional group.
31
0
125678101113141516
CBPR
EOImode
PMHE
PRIbitsIDbits
SEIS
A3V
RES0
Figure B4-3 ICC_CTLR_EL1 bit assignments
RES0, [31:16]
Reserved, RES0.
A3V, [15]
Affinity 3 Valid. The value is:
1 The CPU interface logic supports non-zero values of Affinity 3 in SGI generation
System registers.
SEIS, [14]
SEI Support. The value is:
0 The CPU interface logic does not support local generation of SEIs.
IDbits, [13:11]
Identifier bits. The value is:
0 The number of physical interrupt identifier bits supported is 16 bits.
This field is an alias of ICC_CTLR_EL3.IDbits.
PRIbits, [10:8]
Priority bits. The value is:
0x4 The core supports 32 levels of physical priority with 5 priority bits.
RES0, [7]
Reserved, RES0.
PMHE, [6]
Priority Mask Hint Enable. This bit is read only and is an alias of ICC_CTLR_EL3.PMHE. The
possible values are:
B4 GIC registers
B4.7 ICC_CTLR_EL1, Interrupt Controller Control Register, EL1
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B4-319
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core