B4.7 ICC_CTLR_EL1, Interrupt Controller Control Register, EL1
ICC_CTLR_EL1 controls aspects of the behavior of the GIC CPU interface and provides information
about the features implemented.
Bit field descriptions
ICC_CTLR_EL1 is a 32-bit register and is part of:
• The GIC system registers functional group.
• The GIC control registers functional group.
31
0
125678101113141516
CBPR
EOImode
PMHE
PRIbitsIDbits
SEIS
A3V
RES0
Figure B4-3 ICC_CTLR_EL1 bit assignments
RES0, [31:16]
Reserved, RES0.
A3V, [15]
Affinity 3 Valid. The value is:
1 The CPU interface logic supports non-zero values of Affinity 3 in SGI generation
System registers.
SEIS, [14]
SEI Support. The value is:
0 The CPU interface logic does not support local generation of SEIs.
IDbits, [13:11]
Identifier bits. The value is:
0 The number of physical interrupt identifier bits supported is 16 bits.
This field is an alias of ICC_CTLR_EL3.IDbits.
PRIbits, [10:8]
Priority bits. The value is:
0x4 The core supports 32 levels of physical priority with 5 priority bits.
RES0, [7]
Reserved, RES0.
PMHE, [6]
Priority Mask Hint Enable. This bit is read only and is an alias of ICC_CTLR_EL3.PMHE. The
possible values are:
B4 GIC registers
B4.7 ICC_CTLR_EL1, Interrupt Controller Control Register, EL1
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B4-319
Non-Confidential
To Next Page
Loading...
