ARM Cortex-A76 Core User Manual

D4.1 AArch32 PMU register summary
The PMU counters and their associated control registers are accessible in the AArch32 Execution state
from the internal CP15 system register interface with MCR and MRC instructions for 32-bit registers and
MCRR and MRRC for 64-bit registers.
The following table gives a summary of the Cortex-A76 PMU registers in the AArch32 Execution state.
For those registers not described in this chapter, see the Arm
®
Architecture Reference Manual Armv8, for
Armv8-A architecture profile.
Table D4-1 PMU register summary in the AArch32 Execution state
CRn Op1 CRm Op2 Name Type Width Reset Description
c9 0 c12 0 PMCR RW 32
0x410B30XX
D4.4 PMCR, Performance Monitors Control Register
on page D4-441
c9 0 c12 1 PMCNTENSET RW 32
0x00000000
Performance Monitors Count Enable Set Register
c9 0 c12 2 PMCNTENCLR RW 32
0x00000000
Performance Monitors Count Enable Clear Register
c9 0 c12 3 PMOVSR RW 32
0x00000000
Performance Monitors Overflow Flag Status Register
c9 0 c12 4 PMSWINC WO 32 UNK
Performance Monitors Software Increment Register
c9 0 c12 5 PMSELR RW 32 UNK
Performance Monitors Event Counter Selection
Register
c9 0 c12 6 PMCEID0 RO 32
0x7FFF0F3F
D5.2 PMCEID0_EL0, Performance Monitors Common
Event Identification Register 0, EL0 on page D5-448
c9 0 c12 7 PMCEID1 RO 32
0x0000BE7F
D5.3 PMCEID1_EL0, Performance Monitors Common
Event Identification Register 1, EL0 on page D5-451
c9 0 c14 4 PMCEID2 RO 32
0x00000000
Reserved
c9 0 c14 5 PMCEID3 RO 32
0x00000000
Reserved
c9 0 c13 0 PMCCNTR[31:0] RW 32 UNK
Performance Monitors Cycle Count Register
c9 3 c13 0 PMCCNTR[63:0] RW 64 UNK
c9 0 c13 1 PMXEVTYPER RW 32 UNK Performance Monitors Selected Event Type Register
c9 0 c13 2 PMXEVCNTR RW 32 UNK Performance Monitors Selected Event Count Register
c9 0 c14 0 PMUSERENR RW 32 UNK
Performance Monitors User Enable Register
c9 0 c14 3 PMOVSSET RW 32
0x00000000
Performance Monitor Overflow Flag Status Set
Register
c14 0 c8 0 PMEVCNTR0 RW 32 UNK
Performance Monitor Event Count Registers
c14 0 c8 1 PMEVCNTR1 RW 32 UNK
c14 0 c8 2 PMEVCNTR2 RW 32 UNK
c14 0 c8 3 PMEVCNTR3 RW 32 UNK
c14 0 c8 4 PMEVCNTR4 RW 32 UNK
c14 0 c8 5 PMEVCNTR5 RW 32 UNK
D4 AArch32 PMU registers
D4.1 AArch32 PMU register summary
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D4-434
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core