ARM Cortex-A76 Core

Table D4-1 PMU register summary in the AArch32 Execution state (continued)
CRn Op1 CRm Op2 Name Type Width Reset Description
c14 0 c12 0 PMEVTYPER0 RW 32 UNK
Performance Monitors Event Type Registers
c14 0 c12 1 PMEVTYPER1 RW 32 UNK
c14 0 c12 2 PMEVTYPER2 RW 32 UNK
c14 0 c12 3 PMEVTYPER3 RW 32 UNK
c14 0 c12 4 PMEVTYPER4 RW 32 UNK
c14 0 c12 5 PMEVTYPER5 RW 32 UNK
c14 0 c15 7 PMCCFILTR RW 32 UNK
Performance Monitors Cycle Count Filter Register
D4 AArch32 PMU registers
D4.1 AArch32 PMU register summary
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