ARM Cortex-A76 Core

B2.85 MPIDR_EL1, Multiprocessor Affinity Register, EL1
The MPIDR_EL1 provides an additional core identification mechanism for scheduling purposes in a
cluster.
Bit field descriptions
MPIDR_EL1 is a 64-bit register, and is part of the Other system control registers functional group.
This register is Read Only.
Aff1 Aff0
063 16 15
8 7
Aff2
2324
MT
2930
U
32 31
Aff3
40 39 25
Aff1
11 10
RES0
RES1
Figure B2-69 MPIDR_EL1 bit assignments
RES0, [63:40]
RES0 Reserved.
Aff3, [39:32]
Affinity level 3. Highest level affinity field.
CLUSTERID
Indicates the value read in the CLUSTERIDAFF3 configuration signal.
RES1, [31]
RES1 Reserved.
U, [30]
Indicates a single core system, as distinct from core 0 in a cluster. This value is:
0 Core is part of a multiprocessor system. This is the value for implementations with
more than one core, and for implementations with an ACE or CHI master interface.
RES0, [29:25]
RES0 Reserved.
MT, [24]
Indicates whether the lowest level of affinity consists of logical cores that are implemented
using a multithreading type approach. This value is:
1 Performance of PEs at the lowest affinity level is very interdependent.
Affinity0 represents threads. Cortex-A76 is not multithreaded, but may be in a system
with other cores that are multithreaded.
Aff2, [23:16]
Affinity level 2. Second highest level affinity field.
B2 AArch64 system registers
B2.85 MPIDR_EL1, Multiprocessor Affinity Register, EL1
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B2-267
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