ARM Cortex-A76 Core User Manual

CLUSTERID
Indicates the value read in the CLUSTERIDAFF2 configuration signal.
Aff1, [15:11]
Part of Affinity level 1. Third highest level affinity field.
RAZ Read-As-Zero.
Aff1, [10:8]
Part of Affinity level 1. Third highest level affinity field.
CPUID. Identification number for each CPU in the Cortex-A76 cluster:
0x0 MP1: CPUID: 0.
to
0x7 MP8: CPUID: 7.
Aff0, [7:0]
Affinity level 0. The level identifies individual threads within a multithreaded core. The
Cortex-A76 core is single-threaded, so this field has the value 0x00.
Configurations
MPIDR_EL1[31:0] is mapped to external register EDDEVAFF0.
MPIDR_EL1[63:32] is mapped to external register EDDEVAFF1.
Bit fields and details that are not provided in this description are architecturally defined. See the
Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
B2 AArch64 system registers
B2.85 MPIDR_EL1, Multiprocessor Affinity Register, EL1
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B2-268
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core