D3.10 EDPIDR2, External Debug Peripheral Identification Register 2
The EDPIDR2 provides information to identify an external debug component.
Bit field descriptions
The EDPIDR2 is a 32-bit register.
31 0
34
DES_1
78
Revision
JEDEC
2
RES0
Figure D3-9 EDPIDR2 bit assignments
RES0, [31:8]
RES0 Reserved.
Revision, [7:4]
0 r0p0.
JEDEC, [3]
0b1 RAO. Indicates a JEP106 identity code is used.
DES_1, [2:0]
0b011 Arm Limited. This is the most significant nibble of JEP106 ID code.
Bit fields and details not provided in this description are architecturally defined. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The EDPIDR2 can be accessed through the external debug interface, offset 0xFE8.
D3 Memory-mapped debug registers
D3.10 EDPIDR2, External Debug Peripheral Identification Register 2
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
D3-428
Non-Confidential
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