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ARM Cortex-A76 Core User Manual

ARM Cortex-A76 Core
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B3.10 ERR0STATUS, Error Record Primary Status Register
The ERR0STATUS contains information about the error record:
• Whether any error has been detected.
• Whether any detected error was not corrected and returned to a master.
• Whether any detected error was not corrected and deferred.
• Whether a second error of the same type was detected before software handled the first error.
• Whether any error has been reported.
• Whether the other error record registers contain valid information.
Bit field descriptions
ERR0STATUS is a 32-bit register.
CE SERR
31 30 429
RES0
28 27 26 25 24 23 22 21 20 19 5
UET
PN
DE
AV
V
UE
ER
OF
MV
0
Figure B3-8 ERR0STATUS bit assignments
AV, [31]
Address Valid. The possible values are:
0 ERR0ADDR is not valid.
1 ERR0ADDR contains an address associated with the highest priority error recorded by this
record.
V, [30]
Status Register valid. The possible values are:
0 ERR0STATUS is not valid.
1 ERR0STATUS is valid. At least one error has been recorded.
UE, [29]
Uncorrected error. The possible values are:
0 No error that could not be corrected or deferred has been detected.
1 At least one error that could not be corrected or deferred has been detected. If error recovery
interrupts are enabled, then the interrupt signal is asserted until this bit is cleared.
ER, [28]
Error reported. The possible values are:
0 No external abort has been reported.
1 The node has reported an external abort to the master that is in access or making a
transaction.
B3 Error system registers
B3.10 ERR0STATUS, Error Record Primary Status Register
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B3-307
Non-Confidential

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ARM Cortex-A76 Core Specifications

General IconGeneral
ArchitectureARMv8.2-A
MicroarchitectureCortex-A76
Pipeline Depth13 stages
FrequencyUp to 3.0 GHz
Process Technology7nm
Core TypeOut-of-order
NEONYes
Power EfficiencyImproved over Cortex-A75
Performance Improvement35% over Cortex-A75
Core Count1-4 cores per cluster
ISA SupportAArch64 and AArch32
Branch PredictionYes
L1 Data Cache32KB, per core
L2 Cache256KB or 512KB, per core
L3 CacheUp to 4MB
Memory SupportLPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)DynamIQ Shared Unit (DSU)
Cryptography ExtensionsYes
Virtualization SupportYes
L1 Cache64 KB per core

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