ARM Cortex-A76 Core User Manual

C3.3 AMU counters
The Cortex-A76 core implements five counters, 0-4. The activity monitor counters,
CPUAMEVCNTR0-4, have the following characteristics:
• All events are counted in 64-bit wrapping counters that overflow when they wrap. There is no support
for overflow status indication or interrupts.
• Counters monitoring cycle events do not increment when the core is in WFI or WFE state.
• Events 0, 1, 2, 3, and 4 are fixed, and the CPUAMEVTYPER<n> evtCount bits are read-only.
C3 Activity Monitor Unit
C3.3 AMU counters
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C3-388
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core