ARM Cortex-A76 Core User Manual

B3.4 ERR0FR, Error Record Feature Register
The ERR0FR defines which of the common architecturally defined features are implemented and, of the
implemented features, which are software programmable.
Bit field descriptions
ERR0FR is a 64-bit register, and is part of the Reliability, Availability, Serviceability (RAS) registers
functional group.
The register is Read Only.
63 0
RES0
CEC
123456789101112141516
CFI UE FI UI ED
RP
17181920
CEO DUI
Figure B3-3 ERR0FR bit assignments
[63:20]
RES0
Reserved.
CEO, [19:18]
Corrected Error Overwrite. The value is:
00 Counts CE if a counter is implemented and keeps the previous error status. If the
counter overflows, ERR0STATUS.OF is set to 1.
DUI, [17:16]
Error recovery interrupt for deferred errors. The value is:
00 The core does not support this feature.
RP, [15]
Repeat counter. The value is:
1 A first repeat counter and a second other counter are implemented. The repeat counter
is the same size as the primary error counter.
CEC, [14:12]
Corrected Error Counter. The value is:
010 The node implements an 8-bit standard CE counter in ERR0MISC0[39:32].
CFI, [11:10]
Fault handling interrupt for corrected errors. The value is:
10 The node implements a control for enabling fault handling interrupts on corrected
errors.
UE, [9:8]
In-band uncorrected error reporting. The value is:
01 The node implements in-band uncorrected error reporting, that is external aborts.
FI, [7:6]
B3 Error system registers
B3.4 ERR0FR, Error Record Feature Register
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B3-296
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core