ARM Cortex-A76 Core User Manual

Fault handling interrupt. The value is:
10 The node implements a fault handling interrupt and implements controls for enabling
and disabling.
UI, [5:4]
Error recovery interrupt for uncorrected errors. The value is:
10 The node implements an error recovery interrupt and implements controls for enabling
and disabling.
[3:2]
RES0
Reserved.
ED, [1:0]
Error detection and correction. The value is:
10 The node implements controls for enabling or disabling error detection and correction.
Configurations
ERR0FR resets to 0x000000000000A9A2
ERR0FR is accessible from the following registers when ERRSELR.SEL==0:
B2.40 ERXFR_EL1, Selected Error Record Feature Register, EL1 on page B2-200.
B3 Error system registers
B3.4 ERR0FR, Error Record Feature Register
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B3-297
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core