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ARM Cortex-A76 Core

ARM Cortex-A76 Core
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Fault handling interrupt. The value is:
10 The node implements a fault handling interrupt and implements controls for enabling
and disabling.
UI, [5:4]
Error recovery interrupt for uncorrected errors. The value is:
10 The node implements an error recovery interrupt and implements controls for enabling
and disabling.
[3:2]
RES0
Reserved.
ED, [1:0]
Error detection and correction. The value is:
10 The node implements controls for enabling or disabling error detection and correction.
Configurations
ERR0FR resets to 0x000000000000A9A2
ERR0FR is accessible from the following registers when ERRSELR.SEL==0:
B2.40 ERXFR_EL1, Selected Error Record Feature Register, EL1 on page B2-200.
B3 Error system registers
B3.4 ERR0FR, Error Record Feature Register
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B3-297
Non-Confidential

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