ARM Cortex-A76 Core

D6.7 PMPIDR0, Performance Monitors Peripheral Identification Register 0
The PMPIDR0 provides information to identify a Performance Monitor component.
Bit field descriptions
The PMPIDR0 is a 32-bit register.
31 0
78
Part_0
RES0
Figure D6-6 PMPIDR0 bit assignments
RES0, [31:8]
RES0 Reserved.
Part_0, [7:0]
0x0B Least significant byte of the performance monitor part number.
Bit fields and details not provided in this description are architecturally defined. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The PMPIDR0 can be accessed through the external debug interface, offset 0xFE0.
D6 Memory-mapped PMU registers
D6.7 PMPIDR0, Performance Monitors Peripheral Identification Register 0
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