ARM Cortex-A76 Core User Manual

A4.5 Power control
All power mode transitions are performed at the request of the power controller, using a P-Channel
interface to communicate with the Cortex-A76 core.
There is one P-Channel per core, plus one P-Channel for the cluster. The Cortex-A76 core provides the
current requirements on the PACTIVE signals, so that the power controller can make decisions and
request any change with PREQ and PSTATE. The Cortex-A76 core then performs any actions necessary
to reach the requested power mode, such as gating clocks, flushing caches, or disabling coherency, before
accepting the request.
If the request is not valid, either because of an incorrect transition or because the status has changed so
that state is no longer appropriate, then the request is denied. The power mode of each core can be
independent of other cores in the cluster, however the cluster power mode is linked to the mode of the
cores.
A4 Power management
A4.5 Power control
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A4-52
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core