ARM Cortex-A76 Core User Manual

Exit from WFE low-power state occurs when one of the following occurs:
• The core detects one of the WFE wake-up events.
• The EVENTI input signal is asserted.
• The core detects a reset.
For more information, see the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture
profile.
A4 Power management
A4.4 Architectural clock gating modes
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reserved.
A4-51
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core