ARM Cortex-A76 Core User Manual

B2.4 AArch64 registers by functional group
This section identifies the AArch64 registers by their functional groups and applies to the registers in the
core that are implementation defined or have micro-architectural bit fields. Reset values are provided for
these registers.
Identification registers
Name Type Reset Description
AIDR_EL1 RO
0x00000000
B2.14 AIDR_EL1, Auxiliary ID Register, EL1
on page B2-155
CCSIDR__EL1 RO
- B2.18 CCSIDR_EL1, Cache Size ID Register, EL1
on page B2-159
CLIDR_EL1 RO • 0xC3000123 if L3 cache present.
• 0x82000023 if no L3 cache.
B2.19 CLIDR_EL1, Cache Level ID Register, EL1
on page B2-161
CSSELR_EL1 RW
UNK B2.32 CSSELR_EL1, Cache Size Selection Register, EL1
on page B2-190
CTR_EL0 RO
0x8444C004
B2.33 CTR_EL0, Cache Type Register, EL0 on page B2-191
DCZID_EL0 RO
0x00000004
B2.34 DCZID_EL0, Data Cache Zero ID Register, EL0
on page B2-193
ERRIDR_EL1 RO
0x00000002
B2.36 ERRIDR_EL1, Error ID Register, EL1
on page B2-196
ID_AA64AFR0_EL1 RO
0x00000000
B2.52 ID_AA64AFR0_EL1, AArch64 Auxiliary Feature
Register 0 on page B2-214
ID_AA64AFR1_EL1 RO
0x00000000
B2.53 ID_AA64AFR1_EL1, AArch64 Auxiliary Feature
Register 1 on page B2-215
ID_AA64DFR0_EL1 RO
0x0000000010305408
B2.54 ID_AA64DFR0_EL1, AArch64 Debug Feature
Register 0, EL1 on page B2-216
ID_AA64DFR1_EL1 RO
0x00000000
B2.55 ID_AA64DFR1_EL1, AArch64 Debug Feature
Register 1, EL1 on page B2-218
ID_AA64ISAR0_EL1 RO • 0x0000100010211120 if the
Cryptographic Extension is
implemented.
• 0x0000100010210000 if the
Cryptographic Extension is not
implemented.
B2.56 ID_AA64ISAR0_EL1, AArch64 Instruction Set
Attribute Register 0, EL1 on page B2-219
ID_AA64ISAR1_EL1 RO
0x0000000000100001
B2.57 ID_AA64ISAR1_EL1, AArch64 Instruction Set
Attribute Register 1, EL1 on page B2-221
ID_AA64MMFR0_EL1 RO
0x0000000000101122
B2.58 ID_AA64MMFR0_EL1, AArch64 Memory Model
Feature Register 0, EL1 on page B2-222
ID_AA64MMFR1_EL1 RO
0x0000000010212122
B2.59 ID_AA64MMFR1_EL1, AArch64 Memory Model
Feature Register 1, EL1 on page B2-224
B2 AArch64 system registers
B2.4 AArch64 registers by functional group
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B2-136
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core