ARM Cortex-A76 Core User Manual

(continued)
Name Type Reset Description
ID_AA64MMFR2_EL1 RO
0x0000000000001011
B2.60 ID_AA64MMFR2_EL1, AArch64 Memory Model
Feature Register 2, EL1 on page B2-226
ID_AA64PFR0_EL1 RO • 0x1100000010111112 if the
GICv4 interface is disabled.
• 0x1100000011111112 if the
GICv4 interface is enabled.
B2.61 ID_AA64PFR0_EL1, AArch64 Processor Feature
Register 0, EL1 on page B2-227
ID_AFR0_EL1 RO
0x00000000
B2.63 ID_AFR0_EL1, AArch32 Auxiliary Feature Register
0, EL1 on page B2-230
ID_DFR0_EL1 RO
0x04010088
B2.64 ID_DFR0_EL1, AArch32 Debug Feature Register 0,
EL1 on page B2-231
ID_ISAR0_EL1 RO
0x02101110
B2.65 ID_ISAR0_EL1, AArch32 Instruction Set Attribute
Register 0, EL1 on page B2-233
ID_ISAR1_EL1 RO
0x13112111
B2.66 ID_ISAR1_EL1, AArch32 Instruction Set Attribute
Register 1, EL1 on page B2-235
ID_ISAR2_EL1 RO
0x21232042
B2.67 ID_ISAR2_EL1, AArch32 Instruction Set Attribute
Register 2, EL1 on page B2-237
ID_ISAR3_EL1 RO
0x01112131
B2.68 ID_ISAR3_EL1, AArch32 Instruction Set Attribute
Register 3, EL1 on page B2-239
ID_ISAR4_EL1 RO
0x00010142
B2.69 ID_ISAR4_EL1, AArch32 Instruction Set Attribute
Register 4, EL1 on page B2-241
ID_ISAR5_EL1 RO
0x01011121
ID_ISAR5 has the value 0x01010001
if the Cryptographic Extension is not
implemented and enabled.
B2.70 ID_ISAR5_EL1, AArch32 Instruction Set Attribute
Register 5, EL1 on page B2-243
ID_ISAR6_EL1 RO
0x00000010
B2.71 ID_ISAR6_EL1, AArch32 Instruction Set Attribute
Register 6, EL1 on page B2-245
ID_MMFR0_EL1 RO
0x10201105
B2.72 ID_MMFR0_EL1, AArch32 Memory Model Feature
Register 0, EL1 on page B2-246
ID_MMFR1_EL1 RO
0x40000000
B2.73 ID_MMFR1_EL1, AArch32 Memory Model Feature
Register 1, EL1 on page B2-248
ID_MMFR2_EL1 RO
0x01260000
B2.74 ID_MMFR2_EL1, AArch32 Memory Model Feature
Register 2, EL1 on page B2-250
ID_MMFR3_EL1 RO
0x02122211
B2.75 ID_MMFR3_EL1, AArch32 Memory Model Feature
Register 3, EL1 on page B2-252
ID_MMFR4_EL1 RO
0x00021110
B2.76 ID_MMFR4_EL1, AArch32 Memory Model Feature
Register 4, EL1 on page B2-254
B2 AArch64 system registers
B2.4 AArch64 registers by functional group
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B2-137
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core