ARM Cortex-A76 Core User Manual

(continued)
Name Type Reset Description
ID_PFR0_EL1 RO
0x10010131
B2.77 ID_PFR0_EL1, AArch32 Processor Feature Register
0, EL1 on page B2-256
ID_PFR1_EL1 RO
0x10010000
Bits [31:28] are 0x1 if the GIC CPU
interface is implemented and enabled,
and 0x0 otherwise.
B2.78 ID_PFR1_EL1, AArch32 Processor Feature Register
1, EL1 on page B2-258
ID_PFR2_EL1 RO
0x00000011
B2.79 ID_PFR2_EL1, AArch32 Processor Feature Register
2, EL1 on page B2-260
LORID_EL1 RO
0x0000000000040004
B2.81 LORID_EL1, LORegion ID Register, EL1
on page B2-262
MIDR_EL1 RO
0x413FD0B0
B2.84 MIDR_EL1, Main ID Register, EL1 on page B2-266
MPIDR_EL1 RO
The reset value depends on
CLUSTERIDAFF2[7:0] and
CLUSTERIDAFF3[7:0]. See register
description for details.
B2.85 MPIDR_EL1, Multiprocessor Affinity Register, EL1
on page B2-267
REVIDR_EL1 RO
0x00000000
B2.87 REVIDR_EL1, Revision ID Register, EL1
on page B2-270
VMPIDR_EL2 RW
The reset value is the value of
MPIDR_EL1.
Virtualization Multiprocessor ID Register EL2
VPIDR_EL2 RW
The reset value is the value of
MIDR_EL1.
Virtualization Core ID Register EL2
Other system control registers
Name Type Description
ACTLR_EL1 RW
B2.5 ACTLR_EL1, Auxiliary Control Register, EL1 on page B2-144
ACTLR_EL2 RW
B2.6 ACTLR_EL2, Auxiliary Control Register, EL2 on page B2-145
ACTLR_EL3 RW
B2.7 ACTLR_EL3, Auxiliary Control Register, EL3 on page B2-147
CPACR_EL1 RW
B2.20 CPACR_EL1, Architectural Feature Access Control Register, EL1 on page B2-163
SCTLR_EL1 RW
B2.90 SCTLR_EL1, System Control Register, EL1 on page B2-273
SCTLR_EL2 RW
B2.91 SCTLR_EL2, System Control Register, EL2 on page B2-275
SCTLR_EL3 RW
B2.92 SCTLR_EL3, System Control Register, EL3 on page B2-276
SCTLR_EL12 RW
B2.90 SCTLR_EL1, System Control Register, EL1 on page B2-273
B2 AArch64 system registers
B2.4 AArch64 registers by functional group
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B2-138
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core