ARM Cortex-A76 Core User Manual

Reliability, Availability, Serviceability (RAS) registers
Name Type Description
DISR_EL1 RW
B2.35 DISR_EL1, Deferred Interrupt Status Register, EL1 on page B2-194
ERRIDR_EL1 RW
B2.36 ERRIDR_EL1, Error ID Register, EL1 on page B2-196
ERRSELR_EL1 RW
B2.37 ERRSELR_EL1, Error Record Select Register, EL1 on page B2-197
ERXADDR_EL1 RW
B2.38 ERXADDR_EL1, Selected Error Record Address Register, EL1 on page B2-198
ERXCTLR_EL1 RW
B2.39 ERXCTLR_EL1, Selected Error Record Control Register, EL1 on page B2-199
ERXFR_EL1 RO
B2.40 ERXFR_EL1, Selected Error Record Feature Register, EL1 on page B2-200
ERXMISC0_EL1 RW
B2.41 ERXMISC0_EL1, Selected Error Record Miscellaneous Register 0, EL1 on page B2-201
ERXMISC1_EL1 RW
B2.42 ERXMISC1_EL1, Selected Error Record Miscellaneous Register 1, EL1 on page B2-202
ERXSTATUS_EL1 RW
B2.46 ERXSTATUS_EL1, Selected Error Record Primary Status Register, EL1 on page B2-207
ERXPFGCDNR_EL1 RW
B2.43 ERXPFGCDNR_EL1, Selected Error Pseudo Fault Generation Count Down Register, EL1
on page B2-203
ERXPFCTLR_EL1 RW
B2.44 ERXPFGCTLR_EL1, Selected Error Pseudo Fault Generation Control Register, EL1
on page B2-204
ERXPFGFR_EL1 RO
B2.45 ERXPFGFR_EL1, Selected Pseudo Fault Generation Feature Register, EL1 on page B2-206
HCR_EL2 RW
B2.51 HCR_EL2, Hypervisor Configuration Register, EL2 on page B2-212
VDISR_EL2 RW
B2.101 VDISR_EL2, Virtual Deferred Interrupt Status Register, EL2 on page B2-286
VSESR_EL2 RW
B2.102 VSESR_EL2, Virtual SError Exception Syndrome Register on page B2-287
Virtual Memory control registers
Name Type Description
AMAIR_EL1 RW
B2.15 AMAIR_EL1, Auxiliary Memory Attribute Indirection Register, EL1 on page B2-156
AMAIR_EL2 RW
B2.16 AMAIR_EL2, Auxiliary Memory Attribute Indirection Register, EL2 on page B2-157
AMAIR_EL3 RW
B2.17 AMAIR_EL3, Auxiliary Memory Attribute Indirection Register, EL3 on page B2-158
ATCR_EL1 RW Auxiliary Translation Control Register EL1
ATCR_EL2 RW Auxiliary Translation Control Register EL2
ATCR_EL12 RW Virtual host extension to ATCR_EL1
ATCR_EL3 RW Auxiliary Translation Control Register EL3
AVTCR_EL2 RW Auxiliary Virtualization Translation Control Register EL2
LORC_EL1 RW
B2.80 LORC_EL1, LORegion Control Register, EL1 on page B2-261
LOREA_EL1 RW
LORegion End Address Register EL1
LORID_EL1 RO
B2.81 LORID_EL1, LORegion ID Register, EL1 on page B2-262
B2 AArch64 system registers
B2.4 AArch64 registers by functional group
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
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B2-139
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core