ARM Cortex-A76 Core User Manual

(continued)
Name Type Description
LORN_EL1 RW
B2.82 LORN_EL1, LORegion Number Register, EL1 on page B2-263
LORSA_EL1 RW
LORegion Start Address Register EL1
TCR_EL1 RW
B2.93 TCR_EL1, Translation Control Register, EL1 on page B2-278
TCR_EL2 RW
B2.94 TCR_EL2, Translation Control Register, EL2 on page B2-279
TCR_EL3 RW
B2.95 TCR_EL3, Translation Control Register, EL3 on page B2-280
TTBR0_EL1 RW
B2.96 TTBR0_EL1, Translation Table Base Register 0, EL1 on page B2-281
TTBR0_EL2 RW
B2.97 TTBR0_EL2, Translation Table Base Register 0, EL2 on page B2-282
TTBR0_EL3 RW
B2.98 TTBR0_EL3, Translation Table Base Register 0, EL3 on page B2-283
TTBR1_EL1 RW
B2.99 TTBR1_EL1, Translation Table Base Register 1, EL1 on page B2-284
TTBR1_EL2 RW
B2.100 TTBR1_EL2, Translation Table Base Register 1, EL2 on page B2-285
VTTBR_EL2 RW
B2.104 VTTBR_EL2, Virtualization Translation Table Base Register, EL2 on page B2-289
Virtualization registers
Name Type Description
ACTLR_EL2 RW
B2.6 ACTLR_EL2, Auxiliary Control Register, EL2 on page B2-145
AFSR0_EL2 RW
B2.9 AFSR0_EL2, Auxiliary Fault Status Register 0, EL2 on page B2-150
AFSR1_EL2 RW
B2.12 AFSR1_EL2, Auxiliary Fault Status Register 1, EL2 on page B2-153
AMAIR_EL2 RW
B2.16 AMAIR_EL2, Auxiliary Memory Attribute Indirection Register, EL2 on page B2-157
CPTR_EL2 RW
B2.21 CPTR_EL2, Architectural Feature Trap Register, EL2 on page B2-164
ESR_EL2 RW
B2.48 ESR_EL2, Exception Syndrome Register, EL2 on page B2-209
HACR_EL2 RW
B2.50 HACR_EL2, Hyp Auxiliary Configuration Register, EL2 on page B2-211
HCR_EL2 RW
B2.51 HCR_EL2, Hypervisor Configuration Register, EL2 on page B2-212
HPFAR_EL2 RW
Hypervisor IPA Fault Address Register EL2
TCR_EL2 RW
B2.94 TCR_EL2, Translation Control Register, EL2 on page B2-279
VMPIDR_EL2 RW
Virtualization Multiprocessor ID Register EL2
VPIDR_EL2 RW
Virtualization Core ID Register EL2
VSESR_EL2 RW B2.102 VSESR_EL2, Virtual SError Exception Syndrome Register on page B2-287
VTCR_EL2 RW B2.103 VTCR_EL2, Virtualization Translation Control Register, EL2 on page B2-288
VTTBR_EL2 RW
B2.104 VTTBR_EL2, Virtualization Translation Table Base Register, EL2 on page B2-289
B2 AArch64 system registers
B2.4 AArch64 registers by functional group
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B2-140
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core