ARM Cortex-A76 Core User Manual

Exception and fault handling registers
Name Type Description
AFSR0_EL1 RW
B2.8 AFSR0_EL1, Auxiliary Fault Status Register 0, EL1 on page B2-149
AFSR0_EL2 RW
B2.9 AFSR0_EL2, Auxiliary Fault Status Register 0, EL2 on page B2-150
AFSR0_EL3 RW
B2.10 AFSR0_EL3, Auxiliary Fault Status Register 0, EL3 on page B2-151
AFSR1_EL1 RW
B2.11 AFSR1_EL1, Auxiliary Fault Status Register 1, EL1 on page B2-152
AFSR1_EL2 RW
B2.12 AFSR1_EL2, Auxiliary Fault Status Register 1, EL2 on page B2-153
AFSR1_EL3 RW
B2.13 AFSR1_EL3, Auxiliary Fault Status Register 1, EL3 on page B2-154
DISR_EL1 RW
B2.35 DISR_EL1, Deferred Interrupt Status Register, EL1 on page B2-194
ESR_EL1 RW
B2.47 ESR_EL1, Exception Syndrome Register, EL1 on page B2-208
ESR_EL2 RW
B2.48 ESR_EL2, Exception Syndrome Register, EL2 on page B2-209
ESR_EL3 RW
B2.49 ESR_EL3, Exception Syndrome Register, EL3 on page B2-210
HPFAR_EL2 RW
Hypervisor IPA Fault Address Register EL2
VDISR_EL2 RW
B2.101 VDISR_EL2, Virtual Deferred Interrupt Status Register, EL2 on page B2-286
VSESR_EL2 RW
B2.102 VSESR_EL2, Virtual SError Exception Syndrome Register on page B2-287
Implementation defined registers
Name Type Description
ATCR_EL1 RW Auxiliary Translation Control Register EL1
ATCR_EL2 RW Auxiliary Translation Control Register EL2
ATCR_EL3 RW Auxiliary Translation Control Register EL3
ATCR_EL12 RW Virtual host extension to ATCR_EL1
AVTCR_EL2 RW Auxiliary Virtualization Translation Control Register EL2
CPUACTLR_EL1 RW
B2.23 CPUACTLR_EL1, CPU Auxiliary Control Register, EL1 on page B2-166
CPUACTLR2_EL1 RW
B2.24 CPUACTLR2_EL1, CPU Auxiliary Control Register 2, EL1 on page B2-168
CPUCFR_EL1 RO
B2.25 CPUCFR_EL1, CPU Configuration Register, EL1 on page B2-170
CPUECTLR_EL1 RW
B2.26 CPUECTLR_EL1, CPU Extended Control Register, EL1 on page B2-172
CPUPWRCTLR_EL1 RW
B2.31 CPUPWRCTLR_EL1, Power Control Register, EL1 on page B2-188
ERXPFGCDNR_EL1 RW
B2.43 ERXPFGCDNR_EL1, Selected Error Pseudo Fault Generation Count Down Register, EL1
on page B2-203
ERXPFGCTLR_EL1 RW
B2.44 ERXPFGCTLR_EL1, Selected Error Pseudo Fault Generation Control Register, EL1
on page B2-204
ERXPFGFR_EL1 RW
B2.45 ERXPFGFR_EL1, Selected Pseudo Fault Generation Feature Register, EL1 on page B2-206
B2 AArch64 system registers
B2.4 AArch64 registers by functional group
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B2-141
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core