ARM Cortex-A76 Core User Manual

C2.3 PMU events
The following table shows the events that are generated and the numbers that the PMU uses to reference
the events. The table also shows the bit position of each event on the event bus. Event reference numbers
that are not listed are reserved.
Event
number
PMU
event bus
(to trace)
Event mnemonic Event description
0x0
[00] SW_INCR Software increment. Instruction architecturally executed (condition
code check pass).
0x1
[01] L1I_CACHE_REFILL
L1 instruction cache refill. This event counts any instruction fetch
which misses in the cache.
The following instructions are not counted:
• Cache maintenance instructions.
• Non-cacheable accesses.
0x2
[02] L1I_TLB_REFILL
L1 instruction TLB refill. This event counts any refill of the instruction
L1 TLB from the L2 TLB. This includes refills that result in a
translation fault.
The following instructions are not counted:
• TLB maintenance instructions.
This event counts regardless of whether the MMU is enabled.
0x3
[167] L1D_CACHE_REFILL
L1 data cache refill. This event counts any load or store operation or
page table walk access which causes data to be read from outside the
L1, including accesses which do not allocate into L1.
The following instructions are not counted:
• Cache maintenance instructions and prefetches.
• Stores of an entire cache line, even if they make a coherency
request outside the L1.
• Partial cache line writes which do not allocate into the L1 cache.
• Non-cacheable accesses.
This event counts the sum of L1D_CACHE_REFILL_RD and
L1D_CACHE_REFILL_WR.
0x4
[05:03] L1D_CACHE
L1 data cache access. This event counts any load or store operation or
page table walk access which looks up in the L1 data cache. In
particular, any access which could count the L1D_CACHE_REFILL
event causes this event to count.
The following instructions are not counted:
• Cache maintenance instructions and prefetches.
• Non-cacheable accesses.
This event counts the sum of L1D_CACHE_RD and
L1D_CACHE_WR.
C2 Performance Monitor Unit
C2.3 PMU events
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core