ARM Cortex-A76 Core User Manual

(continued)
Event
number
PMU
event bus
(to trace)
Event mnemonic Event description
0x5
[07:06] L1D_TLB_REFILL L1 data TLB refill. This event counts any refill of the data L1 TLB
from the L2 TLB. This includes refills that result in a translation fault.
The following instructions are not counted:
• TLB maintenance instructions.
This event counts regardless of whether the MMU is enabled.
0x8
[11:08] INST_RETIRED
Instruction architecturally executed. This event counts all retired
instructions, including those that fail their condition check.
0x9
[12] EXC_TAKEN Exception taken.
0x0A
[13] EXC_RETURN Instruction architecturally executed, condition code check pass,
exception return.
0x0B
[156] CID_WRITE_RETIRED
Instruction architecturally executed, condition code check pass, write to
CONTEXTIDR. This event only counts writes to CONTEXTIDR in
AArch32 state, and via the CONTEXTIDR_EL1 mnemonic in
AArch64 state.
The following instructions are not counted:
• Writes to CONTEXTIDR_EL12 and CONTEXTIDR_EL2.
0x10
[14] BR_MIS_PRED
Mispredicted or not predicted branch speculatively executed. This
event counts any predictable branch instruction which is mispredicted
either due to dynamic misprediction or because the MMU is off and the
branches are statically predicted not taken.
0x11
[15] CPU_CYCLES Cycle
0x12
[16] BR_PRED
Predictable branch speculatively executed. This event counts all
predictable branches.
0x13
[19:17] MEM_ACCESS
Data memory access. This event counts memory accesses due to load
or store instructions.
The following instructions are not counted:
• Instruction fetches.
• Cache maintenance instructions.
• Translation table walks or prefetches.
This event counts the sum of MEM_ACCESS_RD and
MEM_ACCESS_WR.
0x14
[20] L1I_CACHE Level 1 instruction cache access or Level 0 Macro-op cache access.
This event counts any instruction fetch which accesses the L1
instruction cache or L0 Macro-op cache.
The following instructions are not counted:
• Cache maintenance instructions.
• Non-cacheable accesses.
C2 Performance Monitor Unit
C2.3 PMU events
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reserved.
C2-375
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core