ARM Cortex-A76 Core User Manual

A5.5 MMU memory accesses
During a translation table walk, the MMU generates accesses. This section describes the specific
behaviors of the core for MMU memory accesses.
A5.5.1 Configuring MMU accesses
By programming the IRGN and ORGN bits, you can configure the MMU to perform translation table
walks in cacheable or non-cacheable regions:
AArch64 Appropriate TCR_ELx register.
If the encoding of both the ORGN and IRGN bits is Write-Back, the data cache lookup is performed and
data is read from the data cache. External memory is accessed, if the ORGN and IRGN bit contain
different attributes, or if the encoding of the ORGN and IRGN bits is Write-Through or Non-cacheable.
A5.5.2 Descriptor hardware update
The core supports hardware update in AArch64 state using hardware management of the access flag and
hardware management of dirty state.
These features are enabled in registers TCR_ELx and VTCR_EL2.
Hardware management of the Access flag is enabled by the following configuration fields:
• TCR_ELx.HA for stage 1 translations.
• VTCR_EL2.HA for stage 2 translations.
Hardware management of dirty state is enabled by the following configuration fields:
• TCR_ELx.HD for stage 1 translations.
• VTCR_EL2.HD for stage 2 translations.
Note
Hardware management of dirty state can only be enabled if hardware management of the Access flag is
enabled.
To support the hardware management of dirty state, the DBM field is added to the translation table
descriptors as part of Armv8.1 architecture.
The core supports hardware update only in outer Write-Back and inner Write-Back memory regions.
If software requests a hardware update in a memory region that is not inner Write-Back or not outer
Write-Back, then the core returns an abort with the following encoding:
• ESR.ELx.DFSC = 0b110001 for Data Aborts in AArch64.
• ESR.ELx.IFSC = 0b110001 for Instruction Aborts in AArch64.
A5 Memory Management Unit
A5.5 MMU memory accesses
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core