ARM Cortex-A76 Core User Manual

D9.44 TRCITIATBINR, Integration Instruction ATB In Register
The TRCITIATBINR reads the state of the input pins described in this section.
Bit field descriptions
The TRCITIATBINR is a 32-bit register.
31 0
AFVALIDM
Reserved
2 1
ATREADYM
Figure D9-42 TRCITIATBINR bit assignments
For all non-reserved bits:
• When an input pin is LOW, the corresponding register bit is 0.
• When an input pin is HIGH, the corresponding register bit is 1.
• The TRCITIATBINR bit values always correspond to the physical state of the input pins.
[31:2]
Reserved. Read undefined.
AFVALIDM, [1]
Returns the value of the AFVALIDMn input pin.
ATREADYM, [0]
Returns the value of the ATREADYMn input pin.
Bit fields and details not provided in this description are architecturally defined. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The TRCITIATBINR can be accessed through the external debug interface, offset 0xEF4.
D9 ETM registers
D9.44 TRCITIATBINR, Integration Instruction ATB In Register
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
D9-554
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core