ARM Cortex-A76 Core User Manual

D9.27 TRCEVENTCTL1R, Event Control 1 Register
The TRCEVENTCTL1R controls the behavior of the events that TRCEVENTCTL0R selects.
Bit field descriptions
The TRCEVENTCTL1R is a 32-bit register.
31 04 358 7
EN
12 11 10
ATB
13
LPOVERRIDE
RES0
Figure D9-25 TRCEVENTCTL1R bit assignments
RES0, [31:13]
RES0 Reserved.
LPOVERRIDE, [12]
Low-power state behavior override:
0 Low-power state behavior unaffected.
1 Low-power state behavior overridden. The resources and Event trace generation are
unaffected by entry to a low-power state.
ATB, [11]
ATB trigger enable:
0 ATB trigger disabled.
1 ATB trigger enabled.
RES0, [10:4]
RES0 Reserved.
EN, [3:0]
One bit per event, to enable generation of an event element in the instruction trace stream when
the selected event occurs:
0 Event does not cause an event element.
1 Event causes an event element.
Bit fields and details not provided in this description are architecturally defined. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The TRCEVENTCTL1R can be accessed through the external debug interface, offset 0x024.
D9 ETM registers
D9.27 TRCEVENTCTL1R, Event Control 1 Register
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core