ARM Cortex-A76 Core User Manual

A4.1 About power management
The Cortex-A76 core provides mechanisms to control both dynamic and static power dissipation.
Dynamic power management includes the following features:
• Architectural clock gating.
• Per-core Dynamic Voltage and Frequency Scaling (DVFS).
Static power management includes the following features:
• Dynamic retention.
• Powerdown.
Related references
A4.3 Power domains on page A4-48
A4.8 Power domain states for power modes on page A4-57
A4.5 Power control on page A4-52
A4.9 Power up and down sequences on page A4-58
A4 Power management
A4.1 About power management
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A4-46
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core