ARM Cortex-A76 Core User Manual

D9.67 TRCSTALLCTLR, Stall Control Register
The TRCSTALLCTLR enables the ETM trace unit to stall the Cortex-A76 core if the ETM trace unit
FIFO overflows.
Bit field descriptions
The TRCSTALLCTLR is a 32-bit register.
31 07 4 389 2 1
ISTALL LEVEL
RES0
Figure D9-64 TRCSTALLCTLR bit assignments
RES0, [31:9]
RES0 Reserved.
ISTALL, [8]
Instruction stall bit. Controls if the trace unit can stall the core when the instruction trace buffer
space is less than LEVEL:
0 The trace unit does not stall the core.
1 The trace unit can stall the core.
RES0, [7:4]
RES0 Reserved.
LEVEL, [3:2]
Threshold level field. The field can support 4 monotonic levels from 0b00 to 0b11, where:
0b00 Zero invasion. This setting has a greater risk of an ETM trace unit FIFO overflow.
0b11 Maximum invasion occurs but there is less risk of a FIFO overflow.
RES0, [1:0]
RES0 Reserved.
Bit fields and details not provided in this description are architecturally defined. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The TRCSTALLCTLR can be accessed through the external debug interface, offset 0x02C.
D9 ETM registers
D9.67 TRCSTALLCTLR, Stall Control Register
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D9-578
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core