ARM Cortex-A76 Core User Manual

B2.21 CPTR_EL2, Architectural Feature Trap Register, EL2
The CPTR_EL2 controls trapping to EL2 for accesses to CPACR, trace functionality and registers
associated with Advanced SIMD and floating-point execution. It also controls EL2 access to this
functionality.
Bit field descriptions
CPTR_EL2 is a 32-bit register, and is part of the Virtualization registers functional group.
31 0
TFPTCPAC
20 1921 10 911
TTA
13 121430
RES0
RES1
Figure B2-17 CPTR_EL2 bit assignments
TTA, [20]
Trap Trace Access.
This bit is not implemented. RES0.
Configurations
RW fields in this register reset to UNKNOWN values.
Bit fields and details that are not provided in this description are architecturally defined. See the
Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
B2 AArch64 system registers
B2.21 CPTR_EL2, Architectural Feature Trap Register, EL2
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B2-164
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core