B2.62 ID_AA64PFR1_EL1, AArch64 Processor Feature Register 1, EL1
The ID_AA64PFR1_EL1 provides additional information about implemented core features in AArch64.
Bit field descriptions
ID_AA64PFR1_EL1 is a 64-bit register, and is part of the Identification registers functional group.
This register is Read Only.
04 38 7
SSBS
63
RES0
Figure B2-46 ID_AA64PFR1_EL1 bit assignments
RES0, [63:8]
RES0 Reserved.
SSBS, [7:4]
PSTATE.SSBS. The possible values are:
0x1 AArch64 provides the PSTATE.SSBS mechanism to mark regions that are Speculative
Store Bypassing Safe (SSBS), but does not implement the MSR/MRS instructions to
directly read and write the PSTATE.SSBS field.
RES0, [3:0]
RES0 Reserved.
Configurations
ID_AA64PFR1_EL1 is architecturally mapped to External register EDPFR.
Bit fields and details that are not provided in this description are architecturally defined. See the
Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
B2 AArch64 system registers
B2.62 ID_AA64PFR1_EL1, AArch64 Processor Feature Register 1, EL1
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B2-229
Non-Confidential
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