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B5.2 FPCR, Floating-point Control Register

The FPCR controls floating-point behavior.

Bit field descriptions

FPCR is a 32-bit register.

31 027 26 25 24 23 22 21

AHP

FZ16

20 19 18

RMode

RES0

Figure B5-1 FPCR bit assignments

RES0, [31:27]

RES0 Reserved.

AHP, [26]

Alternative half-precision control bit. The possible values are:

0 IEEE half-precision format selected. This is the reset value.

1 Alternative half-precision format selected.

DN, [25]

Default NaN mode control bit. The possible values are:

0 NaN operands propagate through to the output of a floating-point operation. This is the

reset value.

1 Any operation involving one or more NaNs returns the Default NaN.

FZ, [24]

Flush-to-zero mode control bit. The possible values are:

0 Flush-to-zero mode disabled. Behavior of the floating-point system is fully compliant

with the IEEE 754 standard. This is the reset value.

1 Flush-to-zero mode enabled.

RMode, [23:22]

Rounding Mode control field. The encoding of this field is:

0b00 Round to Nearest (RN) mode. This is the reset value.

0b01 Round towards Plus Infinity (RP) mode.

0b10 Round towards Minus Infinity (RM) mode.

0b11 Round towards Zero (RZ) mode.

RES0, [21:20]

RES0 Reserved.

B5 Advanced SIMD and floating-point registers

B5.2 FPCR, Floating-point Control Register

reserved.

B5-347

Non-Confidential

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