FZ16, [19]
Flush-to-zero mode control bit on half-precision data-processing instructions. The possible
values are:
0 Flush-to-zero mode disabled. Behavior of the floating-point system is fully compliant
with the IEEE 754 standard. This is the default value.
1 Flush-to-zero mode enabled.
RES0, [18:0]
RES0 Reserved.
Configurations
The named fields in this register map to the equivalent fields in the AArch32 FPSCR. See
B5.8 FPSCR, Floating-Point Status and Control Register on page B5-358.
Usage constraints
Accessing the FPCR
To access the FPCR:
MRS <Xt>, FPCR ; Read FPCR into Xt
MSR FPCR, <Xt> ; Write Xt to FPCR
Register access is encoded as follows:
Table B5-2 FPCR access encoding
op0 op1 CRn CRm op2
11 011 0100 0100 000
Accessibility
This register is accessible as follows:
EL0 EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
RW RW RW RW RW RW
B5 Advanced SIMD and floating-point registers
B5.2 FPCR, Floating-point Control Register
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B5-348
Non-Confidential
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