ARM Cortex-A76 Core User Manual

B2.25 CPUCFR_EL1, CPU Configuration Register, EL1
The CPUCFR_EL1 provides configuration information for the core.
Bit field descriptions
CPUCFR_EL1 is a 32-bit register, and is part of the IMPLEMENTATION DEFINED registers functional group.
This register is Read Only.
31
0
ECC
12
RES0
Figure B2-21 CPUCFR_EL1 bit assignments
RES0, [31:2]
Reserved, RES0.
ECC, [1:0]
Indicates whether ECC is present or not. The possible values are:
00 ECC is not present.
01 ECC is present.
Configurations
There are no configuration notes.
Bit fields and details that are not provided in this description are architecturally defined. See the
Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
Usage constraints
Accessing the CPUCFR_EL1
This register can be read with the MRS instruction using the following syntax:
MRS <Xt>,<systemreg>
To access the CPUCFR_EL1:
MRS <Xt>, CPUCFR_EL1 ; Read CPUCFR_EL1 into Xt
This syntax is encoded with the following settings in the instruction encoding:
<systemreg> op0 op1 CRn CRm op2
S3_0_C15_C0_0 11 000 1111 0000 000
Accessibility
This register is accessible in software as follows:
B2 AArch64 system registers
B2.25 CPUCFR_EL1, CPU Configuration Register, EL1
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B2-170
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core